• DocumentCode
    1539600
  • Title

    On the complexity of parallelizing sequential circuits using the parallel-prefix method

  • Author

    Hadjicostis, Christoforos N.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
  • Volume
    48
  • Issue
    10
  • fYear
    2001
  • fDate
    10/1/2001 12:00:00 AM
  • Firstpage
    1228
  • Lastpage
    1233
  • Abstract
    The parallel-prefix method uses a tree of identical processing nodes to calculate in parallel, the state and output response of a finite-state machine (FSM) to a finite-length input sequence. Traditionally, each computing node in the tree has been required to perform multiplication of binary matrices. In this paper, we show that under appropriate modifications of the input-output mappings at the leaf nodes of the tree, the operation of each node can be reduced to the operation of the unique finite semigroup that is associated with the given FSM. In terms of this view, previous parallel-prefix approaches for sequential circuits have treated the worst case scenario, in which the order of the associated semigroup is exponential in the number of states of the given FSM
  • Keywords
    circuit complexity; finite state machines; parallel processing; sequential circuits; FSM output; complexity; finite-state machine; input-output mappings; leaf nodes; output response; parallel-prefix method; sequential circuits; Automata; Concurrent computing; Parallel processing; Sequential circuits;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7122
  • Type

    jour

  • DOI
    10.1109/81.956018
  • Filename
    956018