• DocumentCode
    1540497
  • Title

    Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InP HEMT technology

  • Author

    Murata, K. ; Sano, K. ; Sano, E. ; Sugitani, S. ; Enoki, T.

  • Author_Institution
    NTT Photonics Labs., Atsugi, Japan
  • Volume
    37
  • Issue
    20
  • fYear
    2001
  • fDate
    9/27/2001 12:00:00 AM
  • Firstpage
    1235
  • Lastpage
    1237
  • Abstract
    A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 231-1 PRBS data signal at 43 Gbit/s
  • Keywords
    HEMT integrated circuits; III-V semiconductors; digital phase locked loops; indium compounds; optical fibre communication; synchronisation; 0.1 micron; 43 Gbit/s; InAlAs-InGaAs-InP; InAlAs/InGaAs/InP HEMT; PRBS signal; clock and data recovery circuit; monolithic integration; optical fibre communication system; phase locked loop;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010837
  • Filename
    956677
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1540497