High resolution ADC system

We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology.