Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations

This paper introduces a novel approach for isolating the failing paths for a fabricated chip. Failing paths are defined as the paths violating the timing constraint at the post-silicon stage, in the presence of process variations. To achieve this goal, a framework is suggested in which, first, a large number of statistically critical paths are extracted at the pre-silicon stage. These paths are those with the highest probability to violate the timing and therefore can form a “good” candidate set for failing paths. Next, a small set of representative paths are selected from those in the candidate set. These selected paths have their delays highly correlated with the delays of the remaining statistically critical paths. By directly measuring the delays of these selected representative paths at the post-silicon stage, the post-silicon delays of the remaining candidate failing paths can be predicted accurately that allows further isolating the failing paths for each fabricated chip. Simulation results show that up to a few thousand candidate failing paths can be accurately predicted using the post-silicon delays of less than 150 representative paths in the presence of more than 1000 independent process parameter variations for the ISCAS89 benchmark circuits. For each fabricated chip, the isolated failing paths are guaranteed to include all the “actual” failing paths in the candidate set. The proportion of the “actual” nonfailing paths from the isolated failing paths is shown to be very small.