DocumentCode :
1541416
Title :
When is 3D 2B?
Author :
Kahng, Andrew B.
Author_Institution :
University of California, San Diego
Volume :
27
Issue :
4
fYear :
2010
Firstpage :
70
Lastpage :
71
Abstract :
A key facet of "More than Moore" scaling comes under the heading of "3D"—the stacking of multiple integrated-circuit dies using through-silicon vias (TSVs). Stacked-die products reached the marketplace decades ago, but with peripheral I/O on individual dies and interchip interconnect on the "side" of the stack. TSVs are a game changer, as this column explains.
Keywords :
TSVs; design and test; interconnects; scaling; through-silicon vias;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2010.92
Filename :
5512527
Link To Document :
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