Fin-Width Dependence of BJT-Based 1T-DRAM Implemented on FinFET

This letter investigates fin-width dependence on single-transistor latch (STL) for bipolar-junction-transistor (BJT)-based 1T-DRAM through experiments. The minimum drain voltage (V_latch) for the activation of a parasitic lateral BJT in SOI FinFET was measured at various gate lengths (L_G´s) and fin widths (W_fin´s). The multiplication factor and current gain of the parasitic BJT in SOI MOSFET are introduced as determinant factors. The experimental results clearly show that the value of V_latch is reduced in a shorter L_G and wider W_fin device. It was found that the nonlocal effect retards the reduction of V_latch as FinFET scales down.