2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms

Author

Agrawal, Pulin ; Milojevic, Dragomir ; Raghavan, Praveen ; Catthoor, Francky ; Van der Perre, Liesbet ; Beyne, Eric ; Varadarajan, Ravi

Author_Institution

IMEC vzw., Leuven, Belgium

fYear

2014

fDate

20-23 May 2014

Firstpage

381

Lastpage

384

Abstract

3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.

Keywords

integrated circuit interconnections; memory architecture; system-on-chip; three-dimensional integrated circuits; 2D integration; 3D integration; 3D stacked IC; 3D-SIC; LTE; WLAN; architecture-technology co-design; data memory organization; memory-on-logic; mobile MPSoC platforms; system architecture level; wireless PHY processing; Integrated circuit interconnections; Memory management; Organizations; Three-dimensional displays; Wireless communication; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831839

Filename

6831839