DocumentCode :
154187
Title :
Foundry TSV integration and manufacturing challenges
Author :
Shun Qiang Gong ; Wei Liu ; Juan Boon Tan ; Bhatkar, Mahesh ; Hai Cong ; Oswald, J. ; Lo, Eric ; Soh Yun Siah
Author_Institution :
Technol. Dev. Dept., GLOBALFOUNDRIES, Singapore, Singapore
fYear :
2014
fDate :
20-23 May 2014
Firstpage :
385
Lastpage :
388
Abstract :
Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.
Keywords :
copper; foundries; integrated circuit interconnections; integrated circuit yield; three-dimensional integrated circuits; 2.5D TSV technology; Cu; die assembly levels; foundry TSV integration; inline defectivity; integrated circuit manufacturing; interposer warpage; oxide liner isolation defects; stress induced failures; wafer warpage; warpage control; yield projection; Foundries; Manufacturing; Monitoring; Redundancy; Silicon; Three-dimensional displays; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4799-5016-4
Type :
conf
DOI :
10.1109/IITC.2014.6831840
Filename :
6831840
Link To Document :
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