A fault-tolerant associative memory with high-speed operation

Author

Bergh, Harald ; Eneland, Johan ; Lundström, Lars-erik

Author_Institution

Ericsson Telecom AB, Stockholm, Sweden

Volume

25

Issue

4

fYear

1990

fDate

8/1/1990 12:00:00 AM

Firstpage

912

Lastpage

919

Abstract

An 8-kb (128-word×64-b) CMOS associative memory with word and bit-parallel operation is described. The highly parallel and pipelined architecture is optimized for high-speed associative operations. The data processing capability is one word/cycle corresponding to 16 MIPS at a typical cycle time of 60 ns. The memory is fault tolerant under software control. A faulty word location in the memory can be made inaccessible by on-chip circuitry. The device is a complete single-chip associative memory with internally controlled addressing and associative data as output

Keywords

CMOS integrated circuits; content-addressable storage; fault tolerant computing; integrated memory circuits; memory architecture; parallel architectures; pipeline processing; 16 MIPS; 60 ns; 8 kbit; CAM; CMOS; bit-parallel operation; fault-tolerant associative memory; high-speed associative operations; internally controlled addressing; on-chip circuitry; parallel architecture; pipelined architecture; single chip memory; software control; word parallel operation; Associative memory; CADCAM; Circuit faults; Computer aided manufacturing; Computer architecture; Data processing; Fault tolerance; Logic devices; Random access memory; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.58283

Filename

58283