DocumentCode :
1542388
Title :
Making Deduction More Effective in SAT Solvers
Author :
Han, Hyojung ; Somenzi, Fabio ; Jin, HoonSang
Author_Institution :
Dept. of Electr., Comput., & Energy Eng., Univ. of Colorado at Boulder, Boulder, CO, USA
Volume :
29
Issue :
8
fYear :
2010
Firstpage :
1271
Lastpage :
1284
Abstract :
Satisfiability (SAT) solvers often benefit from transformations of the formula to be decided that allow them to do more through deduction and decrease their reliance on enumeration. For formulae in conjunctive normal form, subsumed clauses may be removed or partial resolution may be applied. The objectives of simplifying the formula and speeding up the solver are sometimes competing. We characterize existing transformations in terms of their impact on the deductive power of the formula and their effects on the sizes of the implication graphs. For example, we show that variable elimination works by improving implication graphs. We also present two new techniques that try to increase deductive power. The first is a check performed during the computation of resolvents. The second is a new preprocessing algorithm based on distillation that combines simplification and increase of deductive power. Most current SAT solvers apply resolution at various stages to derive new clauses or simplify existing ones. The former happens during conflict analysis, while the latter is usually done during preprocessing. We show how subsumption of the operands by the resolvent can be inexpensively detected during resolution; we then discuss how this detection is used to improve three stages of the SAT solver: variable elimination, clause distillation, and conflict analysis. The “on-the-fly” subsumption check is easily integrated in a SAT solver. In particular, it is compatible with strong conflict analysis and the generation of unsatisfiability proofs. Experiments show the effectiveness of the new techniques.
Keywords :
computability; graph theory; SAT solvers; conjunctive normal form; implication graphs; on-the-fly subsumption check; satisfiability solvers; Costs; Electronic design automation and methodology; Helium; Logic testing; Power engineering and energy; Symbiosis; Timing; CNF; DPLL; SAT; distillation; preprocessing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2010.2049135
Filename :
5512695
Link To Document :
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