DocumentCode :
1542483
Title :
Reduced complexity symbol detectors with parallel structure for ISI channels
Author :
Erfanian, Javan ; Pasupathy, Subbarayan ; Gulak, Glenn
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume :
42
Issue :
234
fYear :
1994
Firstpage :
1661
Lastpage :
1671
Abstract :
The problem of practical realization of the optimal fixed-delay symbol-by-symbol detection algorithm, which is optimum in the sense of minimizing the symbol error probability, given a delay constraint D, is investigated. A fully-parallel structure is developed, and through systematic reformulations of the algorithm, the computational requirements are reduced considerably. In addition, the problems associated with a large dynamic range such as overflow (or underflow) are (practically) removed. A number of approximations are applied to this simplified parallel symbol (SPS) detector that lead to the derivation of suboptimal detectors. One such suboptimal detector is shown to be the same as the minimum-metric Viterbi detector. A brief comparison of the SPS detector and the Viterbi detector shows that the former has a slightly better performance at low values of signal-to-noise ratio (SNR) and the latter performs a smaller number of computations (particularly) at higher values of SNR; otherwise, the two detectors are comparable in performance and complexity
Keywords :
Delay; Detection algorithms; Detectors; Error probability; Intersymbol interference; Java; Maximum likelihood detection; Maximum likelihood estimation; Very large scale integration; Viterbi algorithm;
fLanguage :
English
Journal_Title :
Communications, IEEE Transactions on
Publisher :
ieee
ISSN :
0090-6778
Type :
jour
DOI :
10.1109/TCOMM.1994.582868
Filename :
582868
Link To Document :
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