DocumentCode
154250
Title
Electroless Cu seed on Ru and Co liners in high aspect ratio TSV
Author
Inoue, Fumihiro ; Philipsen, Harold ; van der Veen, M.H. ; Van Huylenbroeck, Stefaan ; Armini, S. ; Struyf, Herbert ; Tanaka, T.
Author_Institution
IMEC, Leuven, Belgium
fYear
2014
fDate
20-23 May 2014
Firstpage
207
Lastpage
210
Abstract
High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.
Keywords
cobalt; copper; electroless deposition; electroplating; integrated circuit metallisation; ruthenium; three-dimensional integrated circuits; Co; Cu; Cu CMP time; ELD; PVD-Cu seed; Ru; Ru-Co liners; TSV metallization process; deposition technique; electrochemical fill; electroless Cu seed seed layers; electroless deposited layers; high aspect ratio TSV; in-field Cu overburden; size 3 mum; size 50 mum; size 600 nm; standard Cu plating process; through-silicon vias; Abstracts; Etching; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International
Conference_Location
San Jose, CA
Print_ISBN
978-1-4799-5016-4
Type
conf
DOI
10.1109/IITC.2014.6831871
Filename
6831871
Link To Document