3D integration technology using hybrid wafer bonding and via-last TSV process

Author

Takeda, Kenji ; Aoki, Masaki

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

2014

fDate

20-23 May 2014

Firstpage

211

Lastpage

214

Abstract

A three-layer-stacked wafer with CMOS devices was fabricated by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings seamless copper bonding in face-to-face (F2F) and back-to-face (B2F) configurations. The low capacitance of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV.

Keywords

CMOS integrated circuits; integrated circuit design; three-dimensional integrated circuits; wafer bonding; 3D integration technology; B2F configurations; CMOS devices; F2F configurations; KOZ; back-to-face configurations; backside-via-last TSV processes; copper-polymer hybrid wafer bonding; face-to-face configurations; keep-out-zone; residual stress; ring-oscillator measurements; seamless copper bonding; size 25 mum; size 7 mum; three-layer-stacked wafer; Bonding; Copper; Polymers; Silicon; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831872

Filename

6831872