Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip