DocumentCode
1542714
Title
Latch-up testing in CMOS IC´s
Author
Menozzi, R. ; Lanzoni, M. ; Fiegna, C. ; Sangiorgi, Enrico ; Riccò, Bruno
Author_Institution
DEIS, Bologna Univ., Italy
Volume
25
Issue
4
fYear
1990
fDate
8/1/1990 12:00:00 AM
Firstpage
1010
Lastpage
1014
Abstract
Experimental data obtained by testing CMOS commercial ICs for latchup by means of automatic test equipment are presented. The results unambiguously show that latchup resistance is strongly influenced by interactions among complex structures within the circuit that are overlooked by widely used testing procedures. In particular, it is shown that both multiple pin excitation and static current loading can significantly decrease the component latchup resistance because of effects taking place within the semiconductor as well as through metal lines
Keywords
CMOS integrated circuits; automatic testing; integrated circuit testing; CMOS; commercial ICs; latch-up testing; latchup resistance; multiple pin excitation; static current loading; Automatic testing; CMOS integrated circuits; CMOS technology; Circuit testing; Design methodology; Flip-flops; Integrated circuit testing; Logic devices; Physics; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.58295
Filename
58295
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