A 1-GHz charge-packet replicator/subtractor circuit for GaAs CCD signal processing

A novel charge-packet replicator/subtractor circuit based on GaAs charge-coupled device (CCD) technology is described. The circuit exhibits linear gain of 0.989 operating at 1-GHz replication frequency, while consuming only several milliwatts of dynamic power. Experimental results for a prototype circuit operating over the frequency range of 1 MHz to 1 GHz are presented. Due to the low parasitic capacitance of the GaAs semi-insulating substrate, the gain is linear and nearly unity. The chip area required for the circuit consists of several CCD gates and a small MESFET. Based on C-V measurements, the dynamic power consumed for the replication/subtraction process (operating with 5-V clock swings) is estimated to be on the order of several milliwatts at 1 GHz where the operation takes place in 1 ns. Design constraints are outlined and compared to experimental results in an effort to explore the tradeoff between speed and gain. The circuit is shown to be relatively insensitive to the precise voltages used during operation