Title :
Simple noise model and low-noise data-output buffer for ultrahigh-speed memories
Author :
Wada, Tomohisa ; Eino, Masanao ; Anami, Kenji
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
12/1/1990 12:00:00 AM
Abstract :
An analytic noise (voltage bounce on chip-internal VCC/GND lines) model for data-output buffers is described. The model indicates that tr (switching time of output transistor) greater than L×G0 (product between the parasitic inductance on VCC/GND lines and the conductance of the output transistor) and small output voltage amplitude are required in order to reduce the noise voltage. The model give VLSI circuit designers a rough estimation of the VCC/CND line noise. A low-noise data-output buffer combined with a voltage down converter (VDC) is proposed. It decreases the peak noise voltage by one-half without degrading the access time
Keywords :
VLSI; buffer circuits; electron device noise; integrated memory circuits; VLSI circuit design; chip-internal VCC/GND lines; data-output buffer; low-noise; noise model; output transistor; parasitic inductance; switching time; ultrahigh-speed memories; voltage down converter; Circuit noise; Circuit simulation; Degradation; Inductance; Kirchhoff´s Law; Noise generators; Noise level; Noise reduction; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
