Design and implementation of an RSFQ switching node for petaflops networks

Author

Yorozu, S. ; Zinoviev, D.Yu. ; Sazaklis, G.

Author_Institution

NEC Corp., Ibaraki, Japan

Volume

9

Issue

2

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

3557

Lastpage

3560

Abstract

This work is part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). A high-bandwidth low-latency switching network (CNET) based on RSFQ logic/memory family comprises the core of the superconductor part of the HTMT system, interconnecting 4,096 processors. We present a preliminary low-level design and partial experimental implementation of a multi-credit RSFQ network switching node with the estimated throughput of 7/spl middot/10/sup 10/ 85-bit-parallel packets per second, service latency of 109 ps, and dissipated power of 4.6 mW.

Keywords

multi-threading; multistage interconnection networks; packet switching; parallel architectures; superconducting processor circuits; 109 ps; 4.6 mW; 85 bit; CNET; RSFQ logic/memory family; RSFQ switching node; dissipated power; high-bandwidth low-latency switching network; hybrid technology multi-threaded architecture; low-level design; multi-credit RSFQ network; petaflops networks; petaflops-scale computer; service latency; throughput; Astronomy; Clocks; Decoding; Delay; National electric code; Packet switching; Payloads; Physics; Shape control; Throughput;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.783798

Filename

783798