• DocumentCode
    1542866
  • Title

    Comments on `A CMOS four-quadrant multiplier´: effects of threshold voltage

  • Author

    Langlois, P.J.

  • Author_Institution
    Kings Coll., London Univ., UK
  • Volume
    25
  • Issue
    6
  • fYear
    1990
  • fDate
    12/1/1990 12:00:00 AM
  • Firstpage
    1595
  • Lastpage
    1597
  • Abstract
    For the original article see ibid., vol.SC-21, no.3, p.430-5 (1986). A CMOS four-quadrant multiplier based on 12 transistors was proposed by K. Bult and H. Wallinga in the above-titled paper using four floating-well transistors to keep VT constant. It is shown analytically by the commenter that the floating wells can be avoided with little penalty on distortion, but with reduction in signal output. A four-transistor multiplier is also analyzed
  • Keywords
    CMOS integrated circuits; analogue circuits; linear integrated circuits; multiplying circuits; CMOS four-quadrant multiplier; analogue multiplier; distortion; floating-well transistors; four-transistor multiplier; signal output-reduction; threshold voltage; Bandwidth; CMOS technology; Equations; FETs; Frequency response; Linear approximation; Operational amplifiers; Silicon; Solid state circuits; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.62198
  • Filename
    62198
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1542866