Title :
System-level variation analysis for interconnection networks
Author :
Chenyun Pan ; Naeemi, Azad
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper analyzes the impact of interconnect variation at the system-level in terms of clock frequency based on a fast and efficient system-level design methodology. Various types of interconnect variations are compared, including the overlay, critical dimension (CD), and inter-layer dielectric variations. The results indicate that the CD variation has a larger impact on the overall clock frequency of the processor, especially for a logic core at a smaller technology node.
Keywords :
clocks; integrated circuit design; integrated circuit interconnections; CD variation; clock frequency; critical dimension; inter-layer dielectric variations; interconnection networks; logic core; overlay; processor; system-level design methodology; system-level variation analysis; technology node; Capacitance; Clocks; Delays; Integrated circuit interconnections; Metals; Systematics; Wires;
Conference_Titel :
Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4799-5016-4
DOI :
10.1109/IITC.2014.6831893