System-level variation analysis for interconnection networks

This paper analyzes the impact of interconnect variation at the system-level in terms of clock frequency based on a fast and efficient system-level design methodology. Various types of interconnect variations are compared, including the overlay, critical dimension (CD), and inter-layer dielectric variations. The results indicate that the CD variation has a larger impact on the overall clock frequency of the processor, especially for a logic core at a smaller technology node.