High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

Author

Nagasawa, S. ; Numata, H. ; Hashimoto, Y. ; Tahara, S.

Author_Institution

Fundamental Res. Labs., NEC Corp., Tsukuba, Japan

Volume

9

Issue

2

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

3708

Lastpage

3713

Abstract

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

Keywords

clocks; random-access storage; superconducting memory circuits; 16 bit; 620 MHz; Josephson RAM; Josephson regulator; fail bit map; high-frequency clock operation; impedance matched line; matrix array; power supply circuit; signal amplifier; transformer; Binary trees; Circuits; Clocks; Current supplies; Frequency; Impedance matching; National electric code; Power supplies; Regulators; Signal design;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.783834

Filename

783834