Monte Carlo and thermal noise analysis of ultra-high-speed high temperature superconductor digital circuits

Author

Jeffery, M. ; Xie, P.Y. ; Whiteley, S.R. ; Van Duzer, T.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

9

Issue

2

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

4095

Lastpage

4098

Abstract

We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.

Keywords

Monte Carlo methods; flip-flops; high-temperature superconductors; integrated circuit modelling; integrated circuit noise; integrated circuit yield; superconducting device noise; superconducting logic circuits; thermal noise; 1 to 150 GHz; 1 to 83 GHz; 40 K; Monte Carlo simulation; RSFQ T flip-flop; bit error rate; parasitic inductance; rapid single flux quantum toggle flip-flop; thermal noise; ultra-high-speed high temperature superconductor digital circuit; yield; Bit error rate; Circuit noise; Circuit simulation; Flip-flops; High temperature superconductors; Inductance; Josephson junctions; Monte Carlo methods; Rapid thermal processing; Superconducting device noise;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.783926

Filename

783926