Optimization of hybrid JJ/CMOS memory operating temperatures

Author

Gupta, D. ; Amrutur, B. ; Terzioglu, E. ; Ghoshal, U. ; Beasley, M.R. ; Horowitz, M.

Author_Institution

Stanford Univ., CA, USA

Volume

7

Issue

2

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

3307

Lastpage

3310

Abstract

A major drawback of present superconducting electronics is the lack of suitable large scale memory. One approach to circumvent this problem is to use semiconducting CMOS memory in conjunction with the fast Josephson junction (JJ) logic. This requires operating the CMOS memory at cryogenic temperatures. The speed of CMOS circuits has been shown to increase at cryogenic temperatures. Further increase in speed can be obtained by using JJ sense circuits in the CMOS memory. Preliminary results show that access time of 1.5 ns should be possible with this hybrid JJ/CMOS approach using 1.2 micron CMOS, and JJ sense and interface circuits. We also report the results of an analysis of the optimal operating temperature of such hybrid memories in conjunction with refrigeration requirements in light of the emerging cryocooler technologies.

Keywords

CMOS memory circuits; cryogenic electronics; superconducting logic circuits; superconductor-semiconductor boundaries; 1.2 micron; 1.5 ns; Josephson junction logic; access time; cryocooler; cryogenic temperature; hybrid memory; interface circuit; operating temperature optimization; refrigeration; semiconducting CMOS memory; sense circuit; superconducting electronics; CMOS logic circuits; CMOS memory circuits; CMOS technology; Cryogenics; Josephson junctions; Large-scale systems; Refrigeration; Semiconductivity; Superconducting logic circuits; Temperature sensors;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.622065

Filename

622065