• DocumentCode
    1544208
  • Title

    A low latency architecture for computing multiplicative inverses and divisions in GF(2m)

  • Author

    Dinh, A.V. ; Bolton, R.J. ; Mason, R.

  • Author_Institution
    Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada
  • Volume
    48
  • Issue
    8
  • fYear
    2001
  • fDate
    8/1/2001 12:00:00 AM
  • Firstpage
    789
  • Lastpage
    793
  • Abstract
    A low latency architecture to compute the multiplicative inverse and division in a finite field GF (2m) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2l) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit
  • Keywords
    Galois fields; VLSI; digital arithmetic; GF (2m) finite field; Galois Field; VLSI architecture; cryptography; division; error correction; latency; multiplicative inverse; Arithmetic; Circuits; Complexity theory; Computer architecture; Delay; Elliptic curve cryptography; Galois fields; Signal processing algorithms; Throughput; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.959871
  • Filename
    959871
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1544208