DocumentCode :
1544563
Title :
Delay time sensitivity in nonlinear monotone RC trees
Author :
Jain, Navneet K. ; Prasad, V.C. ; Bhattacharyya, A.B.
Author_Institution :
Indian Inst. of Technol., New Delhi, India
Volume :
9
Issue :
5
fYear :
1990
fDate :
5/1/1990 12:00:00 AM
Firstpage :
554
Lastpage :
560
Abstract :
The sensitivity of delay time (time required to achieve a given target voltage) at any node of a nonlinear monotone RC tree is studied using the adjoint-network approach. It is shown that the sensitivity of τ with respect to changes in a parameter of the resistors or the capacitors of the tree can be expressed as an integral of the solutions of the network and its adjoint network. Using this integral it is then established that τ increases for some nodes (depending upon location of a node) due to the decrease in a given resistor value, when τ is small. For other nodes τ would decrease. However, if the target voltage is close to the steady-state value then τ decreases for all the nodes
Keywords :
delays; nonlinear network analysis; sensitivity analysis; adjoint-network approach; capacitors; delay time sensitivity; nonlinear monotone RC trees; resistors; Capacitance; Capacitors; Delay effects; Intelligent networks; Inverters; MOS integrated circuits; Resistors; Steady-state; Timing; Voltage;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.55176
Filename :
55176
Link To Document :
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