DocumentCode :
1544587
Title :
A genetic approach to standard cell placement using meta-genetic parameter optimization
Author :
Shahookar, Khushro ; Mazumder, Pinaki
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Volume :
9
Issue :
5
fYear :
1990
fDate :
5/1/1990 12:00:00 AM
Firstpage :
500
Lastpage :
511
Abstract :
The genetic algorithm applies transformations on the chromosonal representation of the physical layout. The algorithm works on a set of configurations constituting a constant-size population. The transformations are performed through crossover operators that generate a new configuration assimilating the characteristics of a pair of configurations existing in the current population. Mutation and inversion operators are also used to increase the diversity of the population, and to avoid premature convergence at local optima. Due to the simultaneous optimization of a large population of configurations, there is a logical concurrency in the search of the solution space which makes the genetic algorithm an extremely efficient optimizer. Three efficient crossover techniques are compared, and the algorithm parameters are optimized for the cell-placement problem by using a meta-genetic process. The resulting algorithm was tested against TimberWolf 3.3 on five industrial circuits consisting of 100-800 cells. The results indicate that a placement comparable in quality can be obtained in about the same execution time as TimberWolf, but the genetic algorithm needs to explore 20-50 times fewer configurations than does TimberWolf
Keywords :
circuit layout CAD; optimisation; CAD; chromosonal representation; computer aided design; constant-size population; crossover operators; genetic algorithm; inversion operators; layout design; meta-genetic parameter optimization; mutation operators; physical layout; standard cell placement; Biological cells; Character generation; Circuit testing; Computational modeling; Concurrent computing; Genetic algorithms; Genetic mutations; Integrated circuit interconnections; Simulated annealing; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.55180
Filename :
55180
Link To Document :
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