Title :
A memory-based architecture for MPEG2 system protocol LSIs
Author :
Inamori, Minoru ; Naganuma, Jiro ; Endo, Makoto
Author_Institution :
NTT Opt. Network Syst. Labs., Kanagawa, Japan
Abstract :
This paper proposes a memory-based architecture implementing the MPEG2 system protocol large scale integrations (LSIs), and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 system protocol for both multiplexing and demultiplexing MPEG2-encoded streams. It consists of a core central processing unit, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software codesign techniques. The LSI´s provide sufficient performance and flexibility for real-time application of the MPEG2 system protocol. They were fabricated with 0.5 /spl mu/m CMOS embedded gate array process technology. They are now in use on MPEG2 codec systems for several multimedia communication and storage services.
Keywords :
CMOS digital integrated circuits; VLSI; audio coding; code standards; codecs; data compression; demultiplexing equipment; digital signal processing chips; hardware-software codesign; large scale integration; memory architecture; multimedia communication; multiplexing equipment; protocols; real-time systems; video coding; 0.5 micron; CMOS embedded gate array process technology; MPEG2 codec systems; MPEG2 system protocol LSI; MPEG2-encoded streams; core central processing unit; dedicated application-specific hardware; demultiplexing; hardware/software codesign techniques; memories; memory-based architecture; multimedia communication; multiplexing; real-time application; Application software; Central Processing Unit; Computer architecture; Demultiplexing; Design optimization; Hardware; Large scale integration; Memory architecture; Protocols; Real time systems;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
