Failure Analysis of Si Nanowire Field-Effect Transistors Subject to Electrostatic Discharge Stresses

Author

Liu, Wen ; Liou, Juin J. ; Jiang, Y. ; Singh, Navab ; Lo, G.Q. ; Chung, J. ; Jeong, Y.H.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA

Volume

31

Issue

9

fYear

2010

Firstpage

915

Lastpage

917

Abstract

The failure mechanisms of silicon nanowire field-effect transistors subject to electrostatic discharge (ESD) stresses are investigated using electrical characterization and microscopy analysis. Current-voltage measurements are carried out before and after the devices are stressed with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester. Depending on the TLP stress level, either a soft or a hard failure can take place in the nanowire devices due to the nondestructive damage or destructive fusing of nanowires and the surrounding gate oxide.

Keywords

electric current measurement; electrostatic discharge; elemental semiconductors; failure analysis; field effect transistors; microscopy; nanowires; voltage measurement; Si nanowire field-effect transistors; current-voltage measurements; electrical characterization; electrostatic discharge stresses; failure analysis; microscopy analysis; transmission line pulsing tester; Current measurement; Electrostatic analysis; Electrostatic discharge; FETs; Failure analysis; Microscopy; Nanoscale devices; Pulse measurements; Silicon; Stress; Degradation; electrostatic discharge (ESD); failure analysis; gate oxide breakdown; nanowire field-effect transistor (NW FET);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2052911

Filename

5518356