Title :
An integrated logical and physical design flow for deep submicron circuits
Author :
Salek, Amir H. ; Lou, Jinan ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fDate :
9/1/1999 12:00:00 AM
Abstract :
This paper presents a set of techniques and a new design flow to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree like clusters, floorplanning, global routing, and timing analysis/budgeting steps, followed by simultaneous technology mapping and linear placement of each cluster. The strength of this approach lies in the dynamic programming-based algorithms used in performing simultaneous technology mapping and linear placement of the logic clusters. The two algorithms we propose, one for exact total (gate plus routing) area minimization and the other for total (gate plus routing) delay minimization, generate a set of noninferior solutions for each cluster enabling designers to perform tradeoffs between total-area and total-delay. Experimental results on large benchmarks prove the effectiveness of the proposed flow
Keywords :
VLSI; circuit layout CAD; circuit optimisation; dynamic programming; integrated circuit layout; logic CAD; logic partitioning; minimisation of switching nets; network routing; timing; VLSI; budgeting; circuit partitioning; deep submicron circuits; dynamic programming-based algorithms; exact total area minimization; floorplanning; gate plus routing; global routing; high-performance logic circuits; integrated logical/physical design flow; large benchmarks; linear placement; logic clusters; simultaneous technology mapping; timing analysis; total delay minimization; tree like clusters; Clustering algorithms; Delay; Heuristic algorithms; Integrated circuit synthesis; Logic circuits; Minimization methods; Partitioning algorithms; Routing; Simultaneous localization and mapping; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
