Slicing floorplans with boundary constraints

Author

Young, F.Y. ; Wong, D.F. ; Yang, Hannah H.

Author_Institution

Dept. of Comput. Sci., Texas Univ., Austin, TX, USA

Volume

18

Issue

9

fYear

1999

fDate

9/1/1999 12:00:00 AM

Firstpage

1385

Lastpage

1389

Abstract

In floorplanning of very large scale integration design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom, or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplan algorithm to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solutions in the simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good

Keywords

VLSI; circuit layout CAD; integrated circuit layout; simulated annealing; Polish expression; VLSI; boundary constraints; floorplans; modules; packing; placement constraints; simulated annealing; slicing floorplan algorithm; very large scale integration design; Benchmark testing; Circuit simulation; Circuit testing; Costs; Design methodology; Integrated circuit interconnections; Runtime; Shape; Simulated annealing; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.784129

Filename

784129