• DocumentCode
    1544965
  • Title

    Comment on "Event suppression by optimizing VHDL programs"

  • Author

    Chang, K.C.

  • Author_Institution
    Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
  • Volume
    18
  • Issue
    9
  • fYear
    1999
  • Firstpage
    1400
  • Lastpage
    1401
  • Abstract
    This paper presents several corrections and comments to the above paper. Errors in the original very high speed integrated circuit hardware descriptive language (VHDL) code are identified. This paper also suggests much simpler optimized VHDL code to achieve the same result.
  • Keywords
    hardware description languages; high level synthesis; optimisation; VHDL code; VHDL programs; event suppression; hardware descriptive language; optimized VHDL code; sensitive event; simulation; very high speed integrated circuit; Clocks; Combinational circuits; Error correction codes; Hardware; Logic circuits; Logic design; Sequential circuits; Signal processing; Signal synthesis; Very high speed integrated circuits;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.784131
  • Filename
    784131
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1544965