The first MAJC microprocessor: a dual CPU system-on-a-chip

Author

Kowalczyk, Andre ; Adler, Victor ; Amir, Chaim ; Chiu, Frank ; Chng, Choon Ping ; De Lange, Willem J. ; Ge, Yuefei ; Ghosh, Subhendra ; Hoang, Tan Canh ; Huang, Baoqing ; Kant, Shree ; Kao, Y.S. ; Khieu, Cong ; Kumar, Suresh ; Lee, Lan ; Liebermensch, Avi

Author_Institution

Sun Microsyst., Palo Alto, CA, USA

Volume

36

Issue

11

fYear

2001

fDate

11/1/2001 12:00:00 AM

Firstpage

1609

Lastpage

1616

Abstract

The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data (SIMD), and chip multiprocessing. The chip integrates two processors, a memory controller, two high-speed parallel I/O interfaces, and a PCI controller. The chip, fabricated in a 0.22-μm CMOS process with six layers of copper interconnect, contains 13 million transistors and operates at 500 MHz. It is packaged in a 624-pin ceramic column grid array using flip-chip assembly technology

Keywords

CMOS digital integrated circuits; flip-chip devices; high-speed integrated circuits; instruction sets; microprocessor chips; parallel architectures; 0.22 micron; 500 MHz; MAJC microprocessor; PCI controller; ceramic column grid array; chip multiprocessing; copper interconnect; dual CPU system-on-a-chip; flip-chip assembly technology; high-speed parallel I/O interfaces; memory controller; single instruction multiple data; very long instruction word; Assembly; CMOS process; CMOS technology; Ceramics; Copper; Microprocessors; Packaging; Process control; System-on-a-chip; VLIW;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.962280

Filename

962280