Title :
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit
Author :
Hinton, Glenn ; Upton, Michael ; Sager, David J. ; Boggs, Darrell ; Carmean, Douglas M. ; Roussel, Patrice ; Chappell, Terry I. ; Fletcher, Thomas D. ; Milshtein, Mark S. ; Sprague, Milo ; Samaan, Samie ; Murray, Robert
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fDate :
11/1/2001 12:00:00 AM
Abstract :
This paper describes the main features and functions of the Pentium(R) 4 processor microarchitecture. We present the front-end of the machine, including its new form of instruction cache called the trace cache, and describe the out-of-order execution engine, including a low latency double-pumped arithmetic logic unit (ALU) that runs at 4 GHz. We also discuss the memory subsystem, including the low-latency Level 1 data cache that is accessed in two clock cycles. We then describe some of the key features that contribute to the Pentium(R) 4 processor´s floating-point and multimedia performance. We provide some key performance numbers for this processor, comparing it to the Pentium(R) III processor
Keywords :
CMOS digital integrated circuits; cache storage; floating point arithmetic; microprocessor chips; multimedia computing; parallel architectures; pipeline processing; 0.18 micron; 4 GHz; CMOS; IA-32 processor; Level 1 data cache; Pentium 4 processor microarchitecture; clock cycles; double-pumped arithmetic logic unit; floating-point performance; instruction cache; integer execution unit; latency; memory subsystem; multimedia performance; out-of-order execution engine; trace cache; CMOS process; Clocks; Delay; Design methodology; Frequency; Logic; Microarchitecture; Pipeline processing; Silicon; Streaming media;
Journal_Title :
Solid-State Circuits, IEEE Journal of
