Title :
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture
Author :
Yamaguchi, Kouichi ; Fukaishi, Muneo ; Sakamoto, Takehiko ; Akiyama, Naoto ; Nakamura, Kazuyuki
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
11/1/2001 12:00:00 AM
Abstract :
An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s×8-channel receiver fabricated with 0.13-μm CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm2. It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within ±5
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; digital phase locked loops; interpolation; microwave receivers; phase detectors; radio receivers; timing circuits; 2.5 GHz; 30 mW; 5 Gbit/s; CMOS receiver; delay compensation technique; delay locked loop; four-phase clock distribution; four-phase clock generator; multiphase clock generator; multiphase clock signal; phase detector; phase interpolation; quadrature clock; scalable no-feedback-loop architecture; CMOS technology; Circuits; Clocks; Delay; Internet; Interpolation; Microprocessors; Phase locked loops; Signal generators; Wire;
Journal_Title :
Solid-State Circuits, IEEE Journal of
