DocumentCode
1545272
Title
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes
Author
Cho, Taehee ; Lee, Yeong-Taek ; Kim, Eun-Cheol ; Lee, Jin-Wook ; Choi, Sunmi ; Lee, Seungjae ; Kim, Dong-Hwan ; Han, Wook-Ghee ; Lim, Young-Ho ; Lee, Jae-Duk ; Choi, Jung-Dal ; Suh, Kang-Deog
Author_Institution
Samsung Electron. Co. Ltd., Kyunggi, South Korea
Volume
36
Issue
11
fYear
2001
fDate
11/1/2001 12:00:00 AM
Firstpage
1700
Lastpage
1706
Abstract
A 116.7-mm2 NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is fabricated with a 0.15-μm CMOS technology. Utilizing simultaneous operation of four independent banks, the device achieves 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes, respectively. The two-step bitline setup scheme suppresses the peak current below 60 mA. The wordline ramping technique avoids program disturbance. The SLC mode uses the 0.5-V incremental step pulse and self-boosting program inhibit scheme to achieve high program performance, and the MLC mode uses 0.15-V incremental step pulse and local self-boosting program inhibit scheme to tightly control the cell threshold voltage Vth distributions. With the small wordline and bitline pitches of 0.3-μm and 0.36-μm, respectively, the cell Vth shift due to the floating gate coupling is about 0.2 V. The read margins between adjacent two program states are optimized resulting in the nonuniform cell Vth distribution for MLC mode
Keywords
CMOS memory circuits; NAND circuits; PLD programming; flash memories; memory architecture; voltage distribution; 1 Gbit; 1.6 MB/s; 512 Mbit; 6.9 MB/s; CMOS technology; EPROM; cell threshold voltage distribution; chip architecture; dual-mode NAND flash memory; floating gate coupling; high program performance; high-performance; incremental step pulse; independent banks; multilevel program cell; multilevel programming; self-boosting program inhibit scheme; simultaneous operation; single-level program cell; two-step bitline setup scheme; wordline ramping technique; CMOS technology; Costs; Coupling circuits; Digital cameras; Flash memory; Nonvolatile memory; Random access memory; Threshold voltage; Throughput; Voltage control;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.962291
Filename
962291
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