DocumentCode
1545304
Title
Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
Author
Osada, Kenichi ; Shin, Jinuk Luke ; Khan, Masood ; Liou, Yude ; Wang, Karl ; Shoji, Kenichi ; Kuroda, Kenichi ; Ikeda, Shuji ; Ishibashi, Koichiro
Author_Institution
Syst. LSI Res. Dept., Hitachi Ltd., Tokyo, Japan
Volume
36
Issue
11
fYear
2001
fDate
11/1/2001 12:00:00 AM
Firstpage
1738
Lastpage
1744
Abstract
A universal-Vdd 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-μm enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V. Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V. The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation
Keywords
CMOS memory circuits; SRAM chips; cache storage; embedded systems; integrated circuit layout; low-power electronics; timing; 0.65 to 2 V; 1.04 GHz; 1.7 mW; 120 MHz; 32 kB; 530 mW; SRAM chips; cache memory; data array; dummy cells; enhanced CMOS technology; four-way-set-associative embedded cache; lithographically symmetrical cell; lower voltage operation; self-timing; tag array; voltage-adapted timing-generation scheme; wider voltage-range operation; CMOS technology; Circuits; Delay lines; Frequency; Microprocessors; Power dissipation; Random access memory; SRAM chips; Testing; Threshold voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.962296
Filename
962296
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