Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers

Author

Wicht, Bernhard ; Paul, Steffen ; Schmitt-Landsiedel, Doris

Author_Institution

Tech. Univ. Munchen, Germany

Volume

36

Issue

11

fYear

2001

fDate

11/1/2001 12:00:00 AM

Firstpage

1745

Lastpage

1755

Abstract

Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512×24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured

Keywords

CMOS integrated circuits; SRAM chips; circuit feedback; high-speed integrated circuits; integrated circuit layout; low-power electronics; multiplexing equipment; 0.18 micron; 1.8 V; 12288 bit; CMOS; SRAM current sense amplifiers; SRAM macro; bitline multiplexer; feedback structure; finite resistance; high-speed operation; layout area penalty; low-voltage applications; performance degradation; signal amplitude; Capacitance; Feedback circuits; Feedback loop; MOSFETs; Multiplexing; Operational amplifiers; Random access memory; Switches; Velocity measurement; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.962297

Filename

962297