Title :
Parasitic capacitance of submicrometer MOSFET´s
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
fDate :
9/1/1999 12:00:00 AM
Abstract :
We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model
Keywords :
MOSFET; capacitance; semiconductor device models; 2D device simulation; Kamchouchi model; parasitic capacitance; submicrometer MOSFET; Analytical models; Boundary conditions; Conductors; Conformal mapping; Electrodes; Geometry; MOSFET circuits; Mathematical model; Parasitic capacitance; Predictive models;
Journal_Title :
Electron Devices, IEEE Transactions on