Title :
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications
Author :
Yoon, Chi-Weon ; Woo, Ramchan ; Kook, Jeonghoon ; Lee, Se-Joong ; Lee, Kangmin ; Hoi-Jun Yeo
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
11/1/2001 12:00:00 AM
Abstract :
A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-μm embedded memory logic (EML) technology. Its area is 84 mm2, and power consumption is 160 mW when all of the functions are activated
Keywords :
coprocessors; decoding; low-power electronics; mobile computing; multimedia computing; reduced instruction set computing; rendering (computer graphics); video signal processing; 0.18 micron; 16 bit; 160 mW; 20 MHz; 32 bit; 3D rendering engine; 7.125 Mbit; 80 MHz; EML technology; MPEG-4 accelerator; RISC; depth-buffer alpha-blending double-buffering; dual-port SRAM; embedded DRAM; embedded memory logic; gouraud-shading features; graphics rendering; hardware accelerators; low-power circuit techniques; mobile applications; multimedia processor; peripheral blocks; power consumption; video decoding; visual SP@L1 decoding; Circuits; Decoding; Energy consumption; Graphics; Hardware; Logic; MPEG 4 Standard; Random access memory; Reduced instruction set computing; Rendering (computer graphics);
Journal_Title :
Solid-State Circuits, IEEE Journal of
