A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel

Author

Wei, Derrick Chunkai ; Sun, Daniel Qicheng ; Abidi, Asad A.

Author_Institution

Silicon Labs. Inc., Austin, TX, USA

Volume

36

Issue

11

fYear

2001

fDate

11/1/2001 12:00:00 AM

Firstpage

1795

Lastpage

1807

Abstract

A decision feedback equalizer (DFE) with digital error detection and correction implements a fixed-delay tree search with depth of 2. The disk-drive read waveform is first equalized to EPR4 for clock recovery and then re-equalized to the DFE target. A mostly analog implementation of this read channel in 0.6-μm CMOS implements a tapped delay-line forward filter with a cascade of track-and-hold circuits and variable transconductors. Using MTR (2,k) code, the compact read channel IC surpasses a conventional EPR4 read channel with Viterbi detector at user densities in the range 2.0-3.0

Keywords

CMOS analogue integrated circuits; decision feedback equalisers; delay filters; delay lock loops; disc drives; error correction; error detection; partial response channels; phase detectors; phase locked loops; sample and hold circuits; synchronisation; tree searching; 300 MHz; MTR (2,k) code; PLL; analog CMOS disk-drive read channel; clock recovery; decision feedback equalizer; digital error detection; disk-drive read waveform; error correction; fixed-delay tree search; phase detector; tapped delay-line forward filter; track-and-hold circuits; variable transconductors; CMOS analog integrated circuits; Clocks; Decision feedback equalizers; Delay; Detectors; Error correction; Filters; Target tracking; Transconductors; Viterbi algorithm;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.962303

Filename

962303