Cognitive Radio Design Challenges and Techniques

Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes the issues related to the design of wideband signal paths and the decades-wide synthesis of carrier frequencies. A new CMOS low-noise amplifier topology for the range of 50 MHz to 10 GHz is introduced that achieves a noise figure of 2.9 to 5.7 dB with a power dissipation of 22 mW. Several multi-decade carrier generation techniques are proposed and a CMOS prototype is presented that exhibits a phase noise of -94 to -120 dBc/Hz at 1-MHz offset while consuming 31 mW.