Title :
A 5 Gbps 0.13
m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links
Author :
Ahmadi, Mahmoud Reza ; Amirkhany, Amir ; Harjani, Ramesh
Author_Institution :
Adv. Micro Devices (AMD), Boxborough, MA, USA
Abstract :
This paper presents a pilot-based clock and data recovery (CDR) technique for high-speed serial link applications where a low-amplitude clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection-locked oscillator and is used to drive the receiver front-end samplers. The performance of the CDR technique is demonstrated using a 5 Gbps differential receiver fabricated in a 0.13 μm IBM CMOS technology. The clock and data recovery circuit implementation has an area of 0.171 mm2 and consumes 11.75 mA from a 1.5 V supply voltage at 5 Gbps. The recovered clock peak-to-peak and RMS jitter at 5 Gbps are less than 10 ps (5%UI) and 1.6 ps (0.8%UI), respectively with an effective CDR loop bandwidth of approximately 28 MHz at a bit-error rate (BER) of 10-12 . The proposed technique simplifies the CDR design and provides data and inter-symbol interference (ISI) independent performance with a small ≈5% pilot voltage overhead to the transmitted data signal.
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; clocks; error statistics; injection locked oscillators; intersymbol interference; receivers; BER; CMOS pilot-based clock and data recovery scheme; IBM CMOS technology; RMS jitter; bit rate 5 Gbit/s; bit-error rate; current 11.75 mA; differential receiver; high-speed serial link; injection-locked oscillator; intersymbol interference; low-amplitude clock signal; receiver front-end samplers; size 0.13 mum; voltage 1.5 V; Bandwidth; Bit error rate; CMOS technology; Circuits; Clocks; Data mining; Injection-locked oscillators; Jitter; Signal design; Voltage; Analog multi-tone; CML D-flip-flop; LC-VCO; NRZ; PAM2; data notch; decision feedback equalizer (DFE); high-Q bandpass filter; injection locked oscillator (ILO); inter-symbol interference (ISI); mixer-based PLL; partial response; pilot-based CDR; plesiosynchronous; timing calibration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2047439