Data-driven self-timed RSFQ digital integrated circuit and system

Author

Deng, Z.J. ; Yoshikawa, N. ; Whiteley, S.R. ; Van Duzer, T.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

7

Issue

2

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

3634

Lastpage

3637

Abstract

A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.

Keywords

asynchronous circuits; clocks; demultiplexing equipment; shift registers; superconducting logic circuits; timing; 20 Gbit/s; 4 bit; RSFQ superconductive digital integrated circuit; asynchronous timing; data-driven self-timing; demultiplexer; high speed digital test system; on-chip clock generator; shift register; Circuit testing; Circuits and systems; Clocks; Digital integrated circuits; Shift registers; Signal generators; Superconducting integrated circuits; Superconductivity; Timing; Uncertainty;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.622205

Filename

622205