DocumentCode :
1545782
Title :
Multiple distributions for biased random test patterns
Author :
Wunderlich, Hans-Joachim
Author_Institution :
Inst. of Comput. Design & Fault-Tolerance, Karlsruhe Univ., West Germany
Volume :
9
Issue :
6
fYear :
1990
fDate :
6/1/1990 12:00:00 AM
Firstpage :
584
Lastpage :
593
Abstract :
The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and tests can be applied with a self-test technique or externally using linear feedback shift registers. Unfortunately, not all circuits are random-testable, because either the fault coverage is too low or the required test length too large. In many cases the random test lengths can be reduced by orders of magnitude using weighted random patterns. However, there are also some circuits for which no single optimal set of weights exists. A set of weights defines a distribution of the random patterns. It is shown that the problem can be solved using several distributions instead of a single one, and an efficient procedure for computing the optimized input probabilities is presented. If a sufficient number of distributions is applied, then all combinational circuits can be tested randomly with moderate test lengths. The patterns can be produced by an external chip, and an optimized test schedule for circuits with a scan path can be obtained. Formulas are derived to determine strong bounds on the probability of detecting all faults
Keywords :
automatic testing; combinatorial circuits; fault location; feedback; integrated circuit testing; shift registers; biased random test patterns; combinational circuits; fault coverage; integrated circuits testing; linear feedback shift registers; self-test technique; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Distributed computing; Integrated circuit testing; Linear feedback shift registers; Processor scheduling; Test pattern generators;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.55187
Filename :
55187
Link To Document :
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