• DocumentCode
    1546038
  • Title

    A Highly Fault-Efficient SAT-Based ATPG Flow

  • Author

    Eggersgluss, Stephan ; Drechsler, Rolf

  • Author_Institution
    German Res. Center for Artificial Intell. (DFKI), Germany
  • Volume
    29
  • Issue
    4
  • fYear
    2012
  • Firstpage
    63
  • Lastpage
    70
  • Abstract
    ATPG based on Boolean Satisfiability (SAT) could be a promising alternative to structural test generation algorithms. This article proposes a SAT-based ATPG flow for generating high quality test patterns while applicable to large industry designs.
  • Keywords
    Boolean functions; automatic test pattern generation; computability; fault diagnosis; logic testing; Boolean satisfiability; automatic test pattern generation; fault-efficient SAT-based ATPG flow; high quality test pattern; industry design; structural test generation algorithm; Algorithm design and analysis; Automatic test pattern generation; Circuit faults; Energy efficiency; Integrated circuit modeling; Logic gates; Robustness; ATPG; Formal Methods; SAT; SAT-based ATPG; Test Generation;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2012.2205479
  • Filename
    6222114
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1546038