DocumentCode :
1546517
Title :
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
Author :
Chou, Wen-Shen ; Huang, Tzu-Chi ; Lee, Yu-Huei ; Yang, Yao-Yi ; Su, Yi-Ping ; Chen, Ke-Horng ; Huang, Chen-Chih ; Lin, Ying-Hsi ; Lee, Chao-Cheng ; Wen, Kuei-Ann ; Hsu, Ying-Chih ; Peng, Yung-Chow ; Hsueh, Fu-Lung
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
47
Issue :
7
fYear :
2012
fDate :
7/1/2012 12:00:00 AM
Firstpage :
1568
Lastpage :
1584
Abstract :
This paper proposes a 55 nm CMOS 12-bit current-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency.
Keywords :
CMOS integrated circuits; digital-analogue conversion; interference suppression; 3S method; CMOS current-steering video digital-to-analog converter; DNL performance; INL; LSB; PO mode; SFDR; SIDO converter; analog circuits; area efficiency; cross-regulation performance; differential nonlinearity performance; digital circuits; dual-DVS control; embedded dynamic voltage scaling system; energy efficiency; finger separating; finger shifting; finger splitting; frequency 1 MHz; high definition video DAC performance; integral nonlinearity; least significant bit; power consumption reduction; power efficiency improvement; power optimized mode; single-inductor dual-output switching converter; size 55 nm; spurious free dynamic range; steady state; switching noise interference suppression; transient state; voltage 1 V; word length 12 bit; Analog circuits; Arrays; Layout; Microprocessors; Noise; Voltage control; DC-DC converter; Single-inductor dual-output (SIDO); differential nonlinearity (DNL); digital to analog converter (DAC); dynamic voltage scaling (DVS); integral nonlinearity (INL); least significant bit (LSB); spurious free dynamic range (SFDR);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2012.2191331
Filename :
6222360
Link To Document :
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