Optimal algorithm for scheduling CBR traffic in ATM switches

A non-blocking input buffered ATM switch that supports CBR and ABR traffic using a TDM scheduler frame is considered. A new TDM scheduler algorithm (largest-first) for CBR traffic is compared with four others, based on the evenness of the distribution of unused timeslots in the scheduling frame. An even distribution of unused slots minimises the average latency and jitter for ABR traffic. Simulation results show that largest-first allocation is the best.