Title :
An architectural co-synthesis algorithm for distributed, embedded computing systems
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fDate :
6/1/1997 12:00:00 AM
Abstract :
Many embedded computers are distributed systems, composed of several heterogeneous processors and communication links of varying speeds and topologies. This paper describes a new, heuristic algorithm which simultaneously synthesizes the hardware and software architectures of a distributed system to meet a performance goal and minimize cost. The hardware architecture of the synthesized system consists of a network of processors of multiple types and arbitrary communication topology; the software architecture consists of an allocation of processes to processors and a schedule for the processes. Most previous work in co-synthesis targets an architectural template, whereas this algorithm can synthesize a distributed system of arbitrary topology. The algorithm works from a technology database which describes the available processors, communication links, I/O devices, and implementations of processes on processors. Previous work had proposed solving this problem by integer linear programming (ILP); our algorithm is much faster than ILP and produces high-quality results.
Keywords :
computer architecture; distributed processing; high level synthesis; real-time systems; I/O devices; allocation; architectural co-synthesis algorithm; communication topology; distributed embedded computing system; hardware architecture; hardware-software codesign; heterogeneous processors; heuristic algorithm; processor network; scheduling; software architecture; technology database; Computer architecture; Costs; Distributed computing; Embedded computing; Hardware; Heuristic algorithms; Network synthesis; Network topology; Software algorithms; Software architecture;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on