Title :
VLSI compressor design with applications to digital neural networks
Author :
Zhang, D. ; Elmasry, M.I.
Author_Institution :
Dept. of Comput. Sci., City Univ. of Hong Kong, Kowloon, Hong Kong
fDate :
6/1/1997 12:00:00 AM
Abstract :
A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. In this paper, such a compressor design based on complex complementary pass-transistor logic (C/sup 2/PL) is presented. Some types of 3-2 compressors in C/sup 2/PL are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressors, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct logic (CDL), our simulations show that the C/sup 2/PL compressors have the best performance in power, delay and number of transistors.
Keywords :
CMOS logic circuits; VLSI; data compression; digital arithmetic; integrated circuit design; logic design; matrix algebra; neural chips; VLSI compressor design; carry propagation; complex complementary pass-transistor logic; data matrix; digital neural networks; high-capacity neural networks; CMOS logic circuits; CMOS technology; Logic design; Logic devices; MOS devices; Neural networks; Neurons; Switches; Very large scale integration; Voltage;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
