Analytical model for switching transitions of submicron CMOS logics

We propose a new analytical model for the switching characteristics of CMOS logics. Our new model, named the Switching Response of CMOS logic by Convolution approach (SRC), can successfully produce the output waveforms under any switching conditions with simple analytical expressions. SRC modeling is a process of transforming CMOS logic into a linear system. This model provides procedures to determine the transfer function and the driving function (input of linear system) of the linear system from given CMOS logic, and then an output waveform, expressed as a third-order equation, is obtained by the convolution of two functions. All parameters in this model are determined in a straightforward manner from given device characteristics and layout geometry without empirical or fitting processes and presimulations. In addition, a delay equation is developed based upon the SRC model. With this delay equation, the delay can be predicted within a few percent differences compared to SPICE simulation results for the wide range of input transition time and output loading capacitance